Simulation is an indispensable verification step before committing an integrated circuit to an expensive manufacturing process. Over the years, a hierarchy of simulation techniques have been developed to keep pace with the growing complexity of integrated circuits. But the need to perform simulations on increasingly large circuits coupled with the growing analog nature of integrated circuit behavior has stretched the limits of conventional simulation methodologies. Circuit-Level simulators, such as SPICE and ASX, provide utmost accuracy, but with excessive memory and time costs which may be prohibitive.
Over the past few decades the number of transistors that can be incorporated into a single integrated circuit (IC) has risen at a dramatic rate. Unfortunately, as the complexity of ICs increases, so does the likelihood of design errors and the difficulty of detecting and identifying those errors. Consequently, designers have become dependent upon simulation programs to predict the behavior of ICs prior to their actual fabrication. These simulation programs make it possible to verify that an IC conforms to logical and timing specifications before committing the vast resources necessary to build it. Lower level simulators utilize more detailed descriptions of the design and provide greater accuracy and flexibility. But these lower level simulators have a lower efficiency, thereby limiting the size of the circuit designs that they can simulate. In contrast, higher level simulators utilize simplified models to represent the behavior of collections of lower level objects. Because they do not consider many of the lower level details, higher level simulators can execute larger designs more efficiently. But higher level simulators have lower accuracy and flexibility. Accordingly, simulation involves tradeoffs and the design process usually includes simulation at many different levels.
Circuit-Level simulators represent the IC as a network of lumped, possibly nonlinear, transistors, resistors, inductors, capacitors, and current and voltage sources. To describe the behavior of this network, Kirchoff's voltage and current laws are used to formulate a system of coupled nonlinear differential equations. This system of equations is solved using time advancement numerical integration. This simulation technique places few restrictions on the circuit topology and utilizes general non-linear transistor models. In addition, the numerical integration procedure allows the computation of the detailed time step by time step behavior of any electrical variable in the circuit. The accuracy of the integration algorithms is limited only by numerical considerations, which are almost always insignificant compared to the precision with which components can be fabricated on an IC. Circuit-Level simulation is flexible and accurate and has proven to be the most general and reliable technique for estimating the transient response of ICs. Because of their detailed accuracy and flexibility, however, Circuit-Level simulators require a large amount of both memory and time. These requirement result from the inefficiency of processing the entire circuit simultaneously. The general models and topologies require algorithms whose execution time grows exponentially with the circuit size, thereby making their use impractical for large ICs.
In an attempt to accelerate the simulation of large ICs, another generation of Circuit-Level simulators has emerged. These simulators use simplified circuit models and decomposition techniques to partition the IC into smaller pieces that can be analyzed independently. Partitioning achieves several results. First, it allows the formulation and analysis of more moderately sized systems of equations. Second, it opens up the possibility of multi-rate simulation (i.e., the selection of different time steps for different portions of the IC). Third, it becomes possible to completely bypass the analysis of latent sub-circuits (i.e., sub-circuits that are not actively switching). In general, this newer generation of Circuit-Level simulators achieves speed-ups of up to two orders of magnitude over their predecessors. Unfortunately, restricted circuit models and reliability problems have impeded widespread acceptance of this newer generation of circuit level simulators. Furthermore their speedups, although impressive, are limited by their use of numerical integration. Time advancement numerical integration requires that time be advanced in steps and the size of these steps is limited by the need to maintain accuracy and stability.
In contrast, a second type of simulator, a Gate-Level simulator, represents the IC as a network of gates at a higher level in the simulator hierarchy. In this simulator, a gate is an object that represents a collection of transistors. The primary advantage of Gate-Level simulation is efficiency. But disadvantages result from the requirement that the circuit must be partitioned into a number of pre-characterized gates. In particular, custom circuit designs often contain structures whose behavior is not easily modeled by pre-characterized gates. Further, the configuration of circuit gate characteristics must usually be performed manually, a step which can be time consuming and prone to error.
Another form of simulator operates on a switch level circuit. The Switch-Level circuit is a network of transistors that are modeled by voltage controlled switches. Each switch has an associated resistance representing the current driving capabilities of the transistor. This switched-resistence model consists of the series combination of a resistor and a voltage controlled switch. Because the circuit is not partitioned into gates, Switch-Level simulators eliminate the manual configuration step and can simulate a wider variety of circuits than Gate-Level simulators. In addition, the Switch-Level simulators execute significantly faster than Circuit-Level simulators. Instead of modeling the behavior of devices using nonlinear models and computing the response of the networks using numerical integration, the Switch-Level simulators model the devices using simple linear device models and compute the response of circuits using moment analysis. Moment analysis has the advantage over time advancement numerical integration in that the response is computed once for all time rather than at numerous points in time. Overall, the primary advantage of Switch-Level simulators is their efficiency, which allows speedups of more than three orders of magnitude. Furthermore, because they restrict the topology of networks, Switch-Level algorithms have complexities which grow linearly with the size of the circuit, making them suitable for large IC simulation. The disadvantage of Switch-level simulators is their inflexibility. Simple switched resistor models are unsuitable for some MOS digital circuits, and for most ECL and BiCMOS circuits. Limitations may arise from the use of overly simplistic transistor models. The Switch-Level model was initially developed for the simulation of MOS circuits, and works well for the static MOS logic which makes up most of the digital MOS ICs. Occasionally, however, there are small portions of an IC whose behavior cannot be modeled well by a network of switches. These portions must be simulated at the Circuit-Level, thus complicating the verification of the design. Accordingly, there remains a need for a model of a component in a circuit that achieves high simulation accuracy without requiring an excessive amount of time or memory.